The present invention relates to integrated circuit devices which are adapted for high voltage applications and, in particular, integrated circuit devices which are manufactured by the use of semiconductor-on-insulator (SOI) technology and which exhibit improved on-state current handling capabilities while maintaining improved off-state voltage breakdown properties.
Prior high voltage transistors have long been used to switch high voltages. When using these devices, it has been necessary to employ an associated control circuit (preferably an integrated circuit in complex applications) to control the switching function of the high voltage transistor. Associated control circuits typically operate at much lower voltages than high voltage transistors. For many practical reasons, including the difference in operating voltages, low voltage control circuits and high voltage transistors had at one time been fabricated in separate devices.
In order to achieve the related goals of maximum packaging efficiency and total part number reduction, it became desirable to fabricate high voltage transistors and associated control circuits in integrated circuits. Fabrication in single integrated circuits requires that the low voltage sections of these circuits be electrically isolated from the high voltage portions, and that the circuits manifest sufficient current handling capability for the given application.
These requirements concern two distinct operating modes of high voltage transistor integrated circuits--the off-state and the on-state. The off-state performance is measured by breakdown voltage capability. The on-state performance is measured by on-resistance and current handling capability. A first problem encountered in high voltage integrated circuits involved voltage breakdown during the off-state of the device. Such problems were caused by inadequate electrical isolation of various component and subcircuit sections, and such devices were prone to catastrophic voltage breakdown into the on-state.
One such method of electrically isolating components within an integrated circuit is the so-called "dielectric isolation" method. In this method, an electrically insulating material, such as silicon dioxide, is used to isolate the individual components operating at different electric potentials. So-called "silicon-on-insulator" (SOI) technology, where "insulator" refers to silicon dioxide and "silicon" refers to a semiconductor layer deposited atop the insulator layer, is one such example of the dielectric isolation method. In this technology the devices are fabricated in a layer of silicon, approximately 0.1-2 microns thick, which is separated from the silicon substrate by a dielectric layer of silicon dioxide typically 0.1-5 microns thick.
A further improvement to the voltage breakdown capability of high voltage integrated circuits was achieved by introduction of a linear doping profile in the thin drift region between the body and drain regions. U.S. Pat. No. 5,300,448 to Merchant et al., which is hereby incorporated by reference in its entirety, discloses a device architecture and fabrication method that achieves particularly high voltage breakdown capabilities, especially in very thin (less than one micron) SOI films. These devices achieve high breakdown voltage capabilities (&gt;700 volts) during the off-state and would provide an attractive design solution for many high voltage applications were it not for a second limitation encountered in instances where the application requires relatively high current handling capability. The subject matter of the present invention particularly concerns further improvements to devices having very thin (less than one micron) SOI films which overcome this limitation by improving their current-and-power-handling capability.
The problems solved and limitations overcome concern the susceptibility of such devices to pinch-off in the thin film layer adjacent to the body region. This problem is particularly pronounced in thin film SOI devices operating in source-follower (source high) applications. One of the important uses for power transistors is in integrated bridge circuits, which are employed to synthesize waveforms of arbitrary shape and frequency. Typical examples are electronic ballasts and motor drives. In such circuits, the source of the upper of the two switches--the source-follower high-side transistor--has to float above ground potential, and may be biased to the highest voltage in the circuit.
When the source electrode is biased positive (Vs) with respect to the substrate (which is at zero, or ground potential), part of the drift region of the device becomes depleted, thus reducing the cross-sectional area available for current flow, so that the on-resistance increases. Moreover, the silicon substrate acts as an electric-field plate which causes the current to saturate at high drain voltages. The depletion layer within the drift region lowers the magnitude of saturated current.
Increasing layer thicknesses uniformly will not increase the power handling capability of the device since it is only in thin film layers that a linear doping profile increases breakdown voltage capability. Such limitations have heretofore limited the usefulness of thin-film SOI devices where relatively high current handling capability was sought.